Are standards compliant Elliptic Curve Cryptosystems feasible on RFID?

With elliptic curve cryptography emerging as a serious alternative, the desired level of security can be attained with significantly smaller key sizes. This makes ECC very attractive for small-footprint devices with limited computational capability, memory and low-bandwidth network connections. However ECC is still considered to be impracticable for very low-end constrained devices like sensor networks and RFID tags. We present a stand-alone highly area optimized ECC processor design for standards compliant binary field curves. We use the fast squarer implementation to construct an addition chain that allows inversion to be computed efficiently. Hence, we propose an affine co-ordinate ASIC implementation of the ECC processor using a modified Montgomery point multiplication method for binary curves ranging from 113−193 bits. An area between 10k and 18k gates on a 0.35um CMOS process is possible for the different curves which makes the design very attractive for enabling ECC in constrained devices.